1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device provided with a high withstand voltage element used for a drive control circuit which operates an induction motor and the like.
2. Description of the Background Art
In the drive control circuit which operates the load such as an induction motor, a first IGBT (Insulated Gate Bipolar Transistor) and a second IGBT are connected in series as a switching element, and the load is connected at the connection point between the first IGBT and the second IGBT. The first IGBT is connected to the high voltage side and the second IGBT is connected to the ground voltage (potential) side. The first IGBT and the second IGBT are alternately turned on and off, the current is supplied to the load in the state where the first IGBT is turned on, and the current is derived from the load in the state where the second IGBT is turned on.
In order to alternately turn on and off the first IGBT and the second IGBT, a first logic circuit is connected to the gate of the first IGBT, and a second logic circuit is connected to the gate of the second IGBT. In the first logic circuit, the potential at the connection point is used as a reference to output the signal for turning on and off the gate of the first IGBT. In the second logic circuit, the ground potential is used as a reference to output the signal for turning on and off the gate of the second IGBT.
Since the potential at the connection point varies between the high voltage potential and the ground potential, particularly, a predetermined level shift circuit using the characteristics of a field-effect transistor is connected to the first logic circuit. In this level shift circuit, the drain of the field-effect transistor is connected to a sense resistance provided in the first logic circuit. Also connected to this drain is a polysilicon resistance. The drain voltage is detected by detecting the current flowing through the polysilicon resistance.
Based on the detected drain voltage, a predetermined voltage is applied to the gate of the field-effect transistor such that the drain current attains an almost constant value. When the field-effect transistor is turned on, a constant drain current flows through the sense resistance. Accordingly, even in the case where the potential at the connection point varies, a constant potential difference occurs between both ends of the sense resistance connected to the drain, and this potential difference is used as a pulse potential to turn on and off the gate of the first IGBT.
With regard to above-described type of the semiconductor device, the sense resistance, the first logic circuit and the like are formed in the high withstand voltage potential island on the semiconductor substrate. In the high withstand voltage potential island, a first RESURF (REduced SURface Field) isolation region is formed so as to surround the first logic circuit and the like to which a high potential is applied, and thus, a high potential is held in the inner peripheral portion in the first RESURF isolation region with respect to the peripheral region.
Furthermore, the field-effect transistor and the polysilicon resistance are formed in a high withstand voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) region adjacent to the high withstand voltage potential island. In the high withstand voltage LDMOS region, a second RESURF region is formed so as to surround the drain electrode which is connected to the sense resistance and is applied with a high potential. The polysilicon resistance is formed on the second RESURF region in the shape of a spiral from the high potential (drain) side.
The circuit detecting the current flowing through the polysilicon resistance, the gate drive circuit applying a predetermined voltage to the gate, and the like are formed in a second logic circuit region disposed in the vicinity of the high withstand voltage potential island and the high withstand voltage LDMOS region. The circuit detecting the current flowing through the polysilicon resistance is connected to the low potential side of the polysilicon resistance. The gate drive circuit is connected to the gate of the field-effect transistor. One of the documents disclosing such a semiconductor device is Japanese Patent Laying-Open No. 09-283716.
With regard to the semiconductor device as described above, in the first logic circuit formed in the high withstand voltage potential island, in order to detect as a logic signal the potential difference occurring between both ends of the sense resistance, the potential of the high withstand voltage potential island should be held at least by the potential difference for the logic signal with respect to the potential of the drain electrode. Accordingly, the high withstand voltage potential island and the high withstand voltage LDMOS region are separately formed in the semiconductor substrate.
The first RESURF region which provides electrical isolation between the high withstand voltage potential island which is applied with a voltage of approximately 600 V and the peripheral region (low potential region) requires an isolation distance (width) of approximately 100 μm or more. Furthermore, the high withstand voltage LDMOS region also requires the second RESURF region which provides electrical isolation between the high withstand voltage LDMOS region and the peripheral region.